Incorporated herein is a computer program listing microfiche appendix of source code used to model an integrated circuit according to the present invention. Copyright, 1993, Advanced Micro Devices, Inc. A portion of the disclosure to this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the "microfiche appendix", as it appears in the Patent and Trademark Office file or records, but otherwise reserves all copyright rights whatsoever.
1. Field of the Invention
This invention relates to an enhanced integrated circuit simulation layout methodology and more particularly to a layout driven performance design methodology which determines optimal sizing of various electronic devices to be placed upon an integrated circuit.
2. Background of the Relevant Art
The process of manufacturing an integrated circuit begins with a logic/circuit sketch of various devices coupled together in a network necessary to accomplish the desired circuit outcome. Each network includes a series of electronic devices having the output node of one device connected to the input node of one or more subsequent devices. Each device is thereby sized to provide adequate drive needed for activating the subsequent connected devices. Sizing of select devices may entail increasing or decreasing circuit gate configuration to meet the desired fan-out load of the subsequent devices.
Devices connected in a network must operate under certain timing and load constraints. Knowledge of load and timing are important in the design of high performance VLSI circuit. While an electronic device may operate perfectly well as a stand-alone device or under certain load constraints, the same device may not operate when coupled to various other devices within a network. For example, when a device is coupled to a known load, the device can be configured to generally propagate a signal from its input node to its output node within an acceptable time period or duration. However, when the same device is coupled to a series of devices within a network, it may not operate at its 10 targeted time duration or speed due to the additional loading seen at its output node. This problem becomes magnified whenever the interconnect between devices is quite large or small. Interconnect or routing carries with it an associated impedance load. Long and thin interconnect lines present a larger impedance than if the lines are short and wide. Moreover, as interconnect length is increased, resistive-capacitive constant also increases thereby slowing the response time of any signal sent through the interconnect. As such, longer interconnect may increase the associated signal time duration causing certain networks to become inoperable under limited time constraints. High speed VLSI process technologies often enjoy smaller device layout, however, they generally have relatively more extensive interconnect placed between devices. The interconnect length may vary drastically depending upon the specific location in which each device is placed within the chip or integrated circuit area.
In an effort to model performance of various networks under load, traditional layout methodologies utilize computer simulation techniques. Computer simulation entails placing an estimated load impedance at the output node of each device. Given the estimated load, a time propagation or duration between activation of input node and output node can be formulated. The estimated load and estimated time duration for each device is thereby presented to the computer as input in order to determine whether or not the various networks or paths can timely produce a desired output (i.e., whether or not they can operate at speed). Various networks which barely exceed the time constraints necessary to produce an output are denoted as "critical networks." Once critical paths have been identified, the designer often tunes or sizes the circuits of selected devices within the paths to ensure all networks, and especially the critical networks, meet the speed performance goal.
The sizing process may involve changing the gate widths or lengths of circuits within each device so that the respective device produces greater or less drive to the estimated load. After specified devices are sized, the resulting network is then physically placed via photolithography onto a wafer. Unfortunately, sizing changes are generally performed without knowledge of where the devices are to be physically located upon or within the integrated circuit area. As such, the designer will not have knowledge of the amount of interconnect coupled between devices. For example, a device at the chip's upper left hand corner which is to connect to a device at the lower right hand corner must have increased drive capability necessary to offset the added load impedance associated with the lengthy interconnect. In VLSI designs, cross-chip interconnect can be several thousand microns or more, thereby adding to the potential variability of the interconnect length. Unless the chip designer can somehow predict or dictate approximately where each device will be physically located upon the chip, he or she cannot accurately determine whether or not each critical network can meet the speed requirements necessary for circuit operation.
Traditional layout methodologies generally involve computer simulation without knowledge of physical layout parameters and/or device locations. After simulation under estimated load and time duration is accomplished, selected devices are sized and a final layout is then sent to the mask shop for processing upon silicon. The designer generally does not know whether the critical networks of the final layout will operate at speed until the first silicon samples are tested. If first silicon does not operate properly, the designer must resize specific circuits and form another final layout for the production of second silicon. Not only is silicon revisions costly, but it is also time consuming. In today's marketplace it is imperative that manufacturers quickly present an operable work product to customers. Thus, marketplace dictates that first silicon be operable at the performance goals set by the designer. Subsequent revisions, which may take several weeks, must be avoided.